1. Technical Field
The present invention relates to semiconductor wafers and methods for testing ferroelectric memory devices.
2. Related Art
Generally, it takes a long time to conduct a reliability test on a semiconductor memory device with a large capacity. For example, when a polarization fatigue test (hereafter referred to as a “fatigue test”) is conducted on a ferroelectric capacitor, the time required for the test on a memory cell of a 1-bit capacity is enormous. Therefore, for example, when a fatigue test is conducted on a ferroelectric memory device with a large capacity (for example, one mega bits or greater), a huge amount of time is required to complete the test.
In a process for manufacturing a semiconductor memory device, processings such as manufacture of a semiconductor wafer, probe test (hereafter referred to as a “P test”), manufacture of semiconductor chips by dicing the semiconductor wafer, packaging of the semiconductor chips, sorting test and reliability test are conducted in this order. In other words, the reliability test is generally conducted after dicing, packaging and other processings. Accordingly, testing cost (including P test and sorting test costs), dicing cost, and package assembling cost have already been incurred before the reliability test is conducted, such that, if any defects are found by the reliability test, the loss in the costs would become substantial, and it takes a long time to obtain the result of the reliability test after the semiconductor wafer has been manufactured. As a result, the cost for manufacturing semiconductor memory devices increases, and it takes a huge amount of time to feedback the reliability test result to the preceding steps.
Also, when a reliability test is conducted for a semiconductor wafer, the test is generally conducted on each of the chips (or 2-4 chips) in the wafer at a time in view of the structure of a probe card. For this reason, it would take a huge amount of time to conduct the reliability test on the entire semiconductor chips included in each semiconductor wafer, and thus the manufacturing cost increases. Moreover, accompanied with further miniaturization of semiconductor devices and an increase in the number of semiconductor chips per wafer by the use of a wafer with a large diameter in the future, there is a possibility that the manufacturing cost would further increase. An example of related art is described in Japanese Laid-open Patent Application JP-A-9-82772.